ext_tools.yosys_interface module¶

ext_tools.yosys_interface.ic3(file_in, flags, top_module, f_call_and_remove=1)¶

Creates a Yosys script that invokes Yosys and performs circuit validation using the sat command.

Parameters:

file_in (str) – The absolute path to the input circuit file containing an SQCC in Verilog or Blif format.
flags (str) – String containing flag parameters for the sat command.
top_module (str) – The name of the input circuit’s top level module.
f_call_and_remove (int, optional) – Flag specifying whether the script should be executed and then removed (1) or not (0). This also has an effect on the return value. Default value is 1.

Returns:

The exit code of the script execution if f_call_and_remove is set to 1, otherwise the absolute path to the script file. The script is not executed in this case.

ext_tools.yosys_interface.readFiles(files, file_out, top_module, f_call_and_remove=1, f_check_hierarchy=1, f_flatten=1, f_opt=1, f_noattr=1)¶

Creates a Yosys script that reads a set of files into Yosys, performs a number of optional checks and optimizations and writes the resulting circuit into another file.

Parameters:

files (list of str) – A list of absolute file paths for circuit files in Verilog of Blif format to read.
file_out (str) – The absolute path to the output file to which the resulting circuit is written in Verilog or Blif format.
top_module (str) – The name of the top level module of the resulting circuit.
f_call_and_remove (int, optional) – Flag specifying whether the script should be executed and then removed (1) or not (0). Default value is 1.
f_check_hierarchy (int, optional) – Flag specifying whether a hierarchy check verifying that top_module is the top level module should be executed (1) or not (0). Default value is (1).
f_flatten (int, optional) – Flag specifying whether the resulting circuit’s hierarchy should be flattened (1) or not. Default value is 1.
f_opt (int, optional) – Flag specifying whether the resulting circuit should be optimized (1) or not (0). Default value is 1.
f_noattr (int, optional) – Flag specifying whether the -noattr flag should be used for writing the resulting circuit to a Verilog file (1) or not (0). Default value is 1.

Returns:

The absolute path of the generated script file. Note that the file will be removed if f_call_and_remove is set to 1.

ext_tools.yosys_interface.verilogToBlif(file_in, file_out, top_module=None, f_call_and_remove=True, f_flatten=False)¶

Creates a Yosys script that converts a Verilog circuit file to Blif format.

Parameters:

file_in (str) – The absolute path to the input circuit file in Verilog format.
file_out (str) – The absolute path to the output circuit file in Blif format.
top_module (str, optional) – The name of the top level module to write to the Blif file. If set to None, the auto-top flag will be used to determine the top module name. Default value is None.
f_call_and_remove (bool, optional) – Flag specifying whether the script should be executed and then removed (True) or not (False). Default value is True.
f_flatten (bool, optional) – Flag specifying whether the resulting circuit in Blif format should be flattened (True) or not (False). Default value is False.

Returns:

The absolute path of the generated script file. Note that the file will be removed if the f_call_and_remove flag is set to True.

ext_tools.yosys_interface.blifToVerilog(file_in, file_out, top_module, f_wideports=True, f_noattr=True, f_call_and_remove=True, f_flatten=False)¶

Creates a Yosys script that converts a Blif circuit file to Verilog: format.

Parameters:

file_in (str) – The absolute path to the input circuit file in Blif format.
file_out (str) – The absolute path to the output circuit file in Verilog format.
top_module (str) – The name of the top level module of the input circuit. Will be used for hierarchy check.
f_wideports (bool, optional) – Flag specifying whether the wideports flag should be used for reading the Blif file (True) or not (False). Default value is True.
f_noattr (bool, optional) – Flag specifying whether the noattr flag should be used for writing the Verilog file (True) or not (False). Default value is True.
f_call_and_remove (bool, optional) – Flag specifying whether the script should be executed and then removed (True) or not (False). Default value is True.
f_flatten (bool, optional) – Flag specifying whether the resulting circuit in Verilog format should be flattened (True) or not (False). Default value is False.

Returns:

The absolute path of the generated script file. Note that the file will be removed if the f_call_and_remove flag is set to True.

ext_tools.yosys_interface.extractAndWriteModule(file_in, file_out, top_module, module, f_noattr=1, f_call_and_remove=1)¶

Creates a Yosys script that reads a Verilog circuit file and writes a single module from that file into another Verilog file.

Parameters:

file_in (str) – The absolute path to the input circuit file in Verilog format.
file_out (str) – The absolute path to the output circuit file in Verilog format.
top_module (str) – The name of the input circuit’s top level module.
module (str) – The name of the module to extract from the input circuit.
f_noattr (int, optional) – Flag specifying whether the noattr flag should be used for writing the resulting Verilog file (1) or not (0). Default value is 1.
f_call_and_remove (int, optional) – Flag specifying whether the script should be executed and then removed (1) or not (0). Default value is 1.

Returns:

The absolute path of the generated script file. Note that the file will be removed if the f_call_and_remove flag is set to 1.

ext_tools.yosys_interface.replaceModules(file_in, file_out, top_module, files_modules, f_noattr=1, f_call_and_remove=1)¶

Creates a Yosys script that reads a circuit file into Yosys, replaces a number of modules from that circuit with modules read from other circuit files and writes the result to another file.

Parameters:

file_in (str) – The absolute path to the input circuit file in Verilog or Blif format.
file_out (str) – The absolute path to the output circuit file in Verilog or Blif format.
top_module (str) – The name of the top level module in the input circuit.
files_modules (list of tuple) – A list containing tuples (file, module) where module is the name of a module in the input circuit to be replaced and file is the absolute path to a circut file containing the replacement module.
f_noattr (int, optional) – Flag specifying whether the noattr flag should be used for writing the resulting circuit (1) or not (0). Default value is 1.
f_call_and_remove (int, optional) – Flag specifying whether the script should be called and then removed (1) or not (0). Default value is 1.

Returns:

The absolute path of the generated script file. Note that the file will be removed if the f_call_and_remove flag is set to 1.

ext_tools.yosys_interface.flattenDesign(file_in, file_out, top_module, f_techmap=1, f_noattr=1, f_call_and_remove=1)¶

Creates a Yosys script that flattens the design hierarchy, i.e. removes modules and subcircuits, of a circuit design.

This may be needed as a design pre-processing step for ABC.

Parameters:

file_in (str) – The absolute path to the input circuit file in Verilog or Blif format.
file_out (str) – The absolute path to the output circuit file in Verilog or Blif format.
top_module (str) – The name of the top level module of the input circuit.
f_techmap (int, optional) – Flag specifying whether the techmap command should be executed before flattening (1) or not (0). Default value is 1.
f_noattr (int, optional) – Flag specifying whether the noattr flag should be used for writing the resulting circuit file (1) or not (0). Default value is 1.
f_call_and_remove (int, optional) – Flag specifying whether the script should be called and then removed (1) or not (0). Default value is 1.

Returns:

The absolute path of the generated script file. Note that the file will be removed if the f_call_and_remove flag is set to 1.

ext_tools.yosys_interface.techmap(file_in, file_out, top_module, f_noattr=1, f_call_and_remove=1)¶

Creates a Yosys script that synthesizes a circuit using the techmap command.

Parameters:

file_in (str) – The absolute path to the input circuit file in Verilog or Blif format.
file_out (str) – The absolute path to the output circuit file in Verilog or Blif format.
top_module (str) – The name of the top level module of the input circuit.
f_noattr (int, optional) – Flag specifying whether the noattr flag should be used for writing the resulting circuit file (1) or not (0). Default value is 1.
f_call_and_remove (int, optional) – Flag specifying whether the script should be called and then removed (1) or not (0). Default value is 1.

Returns:

The absolute path of the generated script file. Note that the file will be removed if the f_call_and_remove flag is set to 1.

ext_tools.yosys_interface.renameModule(file_in, file_out, module, new_module, f_noattr=1, f_call_and_remove=1)¶

Creates a Yosys script that renames a module in a circuit and writes the resulting circuit to a file.

Parameters:

file_in (str) – The absolute path to the input circuit file in Verilog or Blif format.
file_out (str) – The absolute path to the output circuit file in Verilog or Blif format.
module (str) – The name of the module to rename.
new_module (str) – The new name for the module.
f_noattr (int, optional) – Flag specifying whether the noattr flag should be used for writing the resulting circuit file (1) or not (0). Default value is 1.
f_call_and_remove (int, optional) – Flag specifying whether the script should be called and then removed (1) or not (0). Default value is 1.

Returns:

The absolute path of the generated script file. Note that the file will be removed if the f_call_and_remove flag is set to 1.

ext_tools.yosys_interface.generateStat(file_in, file_out, f_call_and_remove=1)¶

Creates a Yosys script that reads a circuit and writes statistics to another file.

Parameters:	file_in (str) – The absolute path to the input circuit file in Verilog or Blif format. file_out (str) – The absolute path to the output circuit file in any writable format. f_call_and_remove (int, optional) – Flag specifying whether the script should be called and then removed (`1`) or not (`0`). Default value is `1`.
Returns:	The absolute path of the generated script file. Note that the file will be removed if the `f_call_and_remove` flag is set to `1`.

ext_tools.yosys_interface.listModules(file_in, top_module, select_pattern='', f_call_and_remove=1)¶

Creates a Yosys script that reads a circuit design file and lists all modules in the circuit.

The module names are stored in a list and can be filtered by a pattern passed to the select command.

Parameters:	file_in (str) – The absolute path to the input circuit file in Verilog format. top_module (str) – The name of the top level module of the input circuit. select_pattern (str, optional) – The pattern by which to filter the module names. If not empty, the pattern is passed to the `select` command. Default value is `""`. f_call_and_remove (int, optional) – Flag specifying whether the script should be called and then removed (`1`) or not (`0`). Default value is `1`.
Returns:	A list containing all module names in the input circuit matching the `select_pattern`.
Return type:	list of str

ext_tools.yosys_interface.runScript(file, f_run_quiet=1, f_call_and_remove=0)¶

Invokes Yosys and runs a script file using a subprocess call.

Parameters:

file (str) – The absolute path to the script file to execute.
f_run_quiet (int, optional) – Flag specifying whether the script shall be executed in quiet mode (i.e. with flag -qq) (1) or print all messages (i.e. with flag -QT) (0). Default value is 1.
f_call_and_remove (int, optional) – Flag specifying whether the script file shall be removed after execution (1) or not (0). Default value is 0.

Returns:

The exit code of the subprocess call.