# ext_tools.abc_interface module¶

ext_tools.abc_interface.generateStat(file_in, file_out)

Invokes ABC and generates statistics about a circuit using the command print_stats -lmpg.

Parameters: file_in (str) – The absolute path to the input circuit file in Verilog or Blif format. file_out (str) – The absolute path to the output file in any writable format.
ext_tools.abc_interface.opt(file_in, file_out)

Invokes ABC and optimizes a given circuit design.

Parameters: file_in (str) – The absolute path to the circuit file to optimize. file_out (str) – The absolute path to the output file to which the optimized circuit will be written.

Note

If a hierarchy is found in the design it will be flattened, i.e., only the top module remains. This is important if, in later steps, modules should be replaced.

ext_tools.abc_interface.aigRewriting(qc_file, file_in, file_out, effort=2)

Invokes ABC and performs AIG-Rewriting on a given circuit and conforming to given quality constraints.

Parameters: qc_file (str) – The absolute path to the file specifying the quality constraints. Passed to the aig_rewrite command as first parameter. file_in (str) – The absolute path to the input circuit file. Passed to the aig_rewrite command as second parameter. file_out (str) – The absolute path to the output file to which the resulting circuit will be written. effort (int, optional) – Integer in [0..2] specifying the effort level to be used for approximation. Is passed to the aig_rewrite command as -E parameter. Default value is 2. The number of changes as returned by the aig_rewrite command. IOError – If ABC does not behave as expected.
ext_tools.abc_interface.precisionScaling(file_in, file_out, mask)

Invokes ABC and performs precision scaling on a given circuit design.

Parameters: file_in (str) – The absolute path to the input circuit file. file_out (str) – The absolute path to the output file to which the resulting circuit will be written. mask (str) – A string representing the bit mask to be used for precision scaling. It is passed to the precision_scaling command as the only parameter and must be formatted correctly for this purpose. Ideally, the string contains only 0s and 1s and its length equals the number of primary outputs of the input circuit. The number of changes computed as n_start - n_end from the numbers of starting and ending nodes returned by the precision_scaling command. IOError – If ABC does not behave as expected.
ext_tools.abc_interface.dprove(file_in)

Invokes ABC and performs temporal induction to prove sequential equivalence using the dprove command.

Parameters: file_in (str) – The absolute path to the input circuit containing an SQCC in Verilog or Blif format. 1 if the proof was successful, 0 otherwise.
ext_tools.abc_interface.pdr(file_in)

Invokes ABC and performs temporal induction to prove sequential equivalence using the pdr command.

Parameters: file_in (str) – The absolute path to the input circuit containing an SQCC in Verilog or Blif format. 1 if the proof was successful, 0 otherwise.
ext_tools.abc_interface.runCmd(cmd)

Invokes ACB and runs a command using subprocess. The command’s return code is returned.

ext_tools.abc_interface.runScript(file)

Invokes ABC and runs a script file using subprocess. The script’s return code is returned.