Note

This is a WIP Beta version. All content is subject to change.

External programs and frameworks

ABC

ABC is an open-source synthesis tool developed by Berkeley Logic Synthesis and Verification Group. In CIRCA approximation techniques are implemented using ABC.

Yosys

Yosys is developed by Clifford Wolf from TU Vienna. In CIRCA it is used for the synthesis of Verilog files to BLIF netlists.