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External programs and frameworks
================================
.. _ext_progs_abc:
ABC
--------------------
`ABC `_ is an open-source synthesis tool developed by Berkeley Logic Synthesis and Verification Group. In CIRCA approximation techniques are implemented using ABC.
.. _ext_progs_yosys:
Yosys
--------------------
`Yosys `_ is developed by Clifford Wolf from TU Vienna. In CIRCA it is used for the synthesis of Verilog files to BLIF netlists.