# ext_tools.iverilog_interface module¶

ext_tools.iverilog_interface.compileVerilog(source_files, compiled_file, top_module='')

Compiles a list of Verilog files to a file that is executable by the vvp command.

The files must be in Verilog format and include all modules that are instantiated. The name of the root module can be specified. It must be specified if the design hierarchy does not have a unique top level module.

Parameters: source_files (list of str) – A list containing the absolute paths to all Verilog source files. compiled_file (str) – The absolute path to the compiled and executable simulation file. Standard format is *.vvp. top_module (str, optional) – The name of the module to use as root module to execute. Only this module will be simulated when running the compiled simulation file. ValueError – If no source files are specified. RuntimeError – If the iverilog command exits with an error.
ext_tools.iverilog_interface.compileVerilogFileList(source_list_file, compiled_file, top_module='')

Compiles a list of Verilog files specified in a separate file to a simulation file that is executable by the vvp command.

The files must be in Verilog format and include all modules that are instantiated. The name of the root module can be specified. It must be specified if the design hierarchy does not have a unique top level module.

Parameters: source_list_file (str) – The absolute path to the file in which the Verilog source files are listed. This file must be a readable text file that specifies one source file per line and ends with a blank line (!). compiled_file (str) – The absolute path to the compiled and executable simulation file. Standard format is *.vvp. top_module (str, optional) – The name of the module to use as root module to execute. Only this module will be simulated when running the compiled simulation file. RuntimeError – If the iverilog command exits with an error.
ext_tools.iverilog_interface.compileVerilogMixed(source_files, source_list_file, compiled_file, top_module='')
Compiles a list of Verilog files to a file that is executable by the
vvp command.

Source file names can be specified explicitly or by a file containing one source file name per line. The files must be in Verilog format and include all modules that are instantiated. The name of the root module can be specified. It must be specified if the design hierarchy does not have a unique top level module.

Parameters: source_files (list of str) – A list containing the absolute paths to Verilog source files. source_list_file (str) – The absolute path to the file in which other Verilog source files are listed. This file must be a readable text file that specifies one source file per line and ends with a blank line (!). compiled_file (str) – The absolute path to the compiled and executable simulation file. Standard format is *.vvp. top_module (str, optional) – The name of the module to use as root module to execute. Only this module will be simulated when running the compiled simulation file. RuntimeError – If the iverilog command exits with an error.
ext_tools.iverilog_interface.runCompiledVerilog(compiled_file, remove_file=False)

Runs a compiled Verilog simulation file using the vvp command.

Parameters: compiled_file (str) – The absolute path to the compiled simulation file. By convention, simulation files have the format *.vvp. remove_file (bool) – Flag specifying whether the compiled file should be removed after the simulation was executed. Default value is False. RuntimeError – If the vvp command exits with an error.