quality_assurance.quality_assurance_abc_dprove module¶

class quality_assurance.quality_assurance_abc_dprove.ABCDprove(settings)¶

Bases: circa.stages.quality_assurance.quality_assurance.QualityAssurance

QualityAssurance subclass using the dprove command of ABC for circuit validation.

SUPPORTED_CIRCUIT_TYPES = ['combinational', 'run_to_completion', 'streaming']¶

SUPPORTED_ERROR_METRICS = ['BF', 'WC']¶

C_SQCC_TOP_MODULE = 'sqcc'¶

top_module¶

The name of the input circuit’s top level module.

Type:	str

setup(gen_info)¶

Sets up the QualityAssurance instance using a GeneralInformation instance. Provides default implementation

Parameters:	gen_info (`GeneralInformation`) – The framework’s GeneralInformation instance.

validateCircuit(node)¶

Validates the circuit represented by a Node by trying to verify that the circuit meets all its quality constraints.

Parameters:	node (`Node`) – The Node to validate.
Returns:	`True` if the circuit of the given Node is valid, otherwise `False`.
Return type:	bool

_addCutToSqcc(node, test_design)¶

Adds the circuit to be validated to the SQCC and writes it into a file.

Parameters:	node (`Node`) – The Node instance representing the circuit to validate. test_design (str) – The absolute path to the circuit file in which the SQCC will be stored in Verilog or Blif format.

_setupSQCC()¶

Creates and writes the SQCC file implementing a QEC with the global quality constraints specified in the config. The input circuit is flattened and inserted as reference circuit.

Returns:	The absolute path to the SQCC circuit file in Verilog format.
Return type:	str

_writeSqcc()¶

Writes the SQCC file template into which the input circuit and the QEC will be inserted and returns its file name. Modules have to be loaded afterwards.

Returns:	The absolute path to the SQCC circuit file in Verilog format.
Return type:	str

_setupQec()¶

Writes a quality evaluation circuit implementing the global quality constraints specified in the config to a file and returns its file name.

Returns:	The absolute path to the QEC circuit file in Verilog format.
Return type:	str
Raises:	`ValueError` – If relative error is used in the quality constraints (Relative error is not supported yet).

_prepareQecWrapper()¶

Exchanges regexes with information gathered from the original circuit.

Returns:	Content of the modified QEC file as a string.
Return type:	str

_prepareWcQc(msb_0, lsb_1, msb_1, error_wc, is_signed, mod_suffix='')¶

Loads template for worst-case QC and parses regexes.

Returns:	Content of the modified QC file as a string.
Return type:	str

_prepareRelErrQc(msb_0, lsb_1, msb_1, lower_bound, upper_bound, mod_suffix='')¶

Loads template for relative error QC and parses regexes.

Returns:	Content of the modified QC file as a string.
Return type:	str

_prepareBitFlipErrQc(msb_0, lsb_1, msb_1, max_bit_flip, mod_suffix='')¶

Loads template for bit flip error QC and parses regexes.

Returns:	Content of the modified QC file as a string.
Return type:	str

static _findAndReplace(file, repl_pairs)¶

Replaces all occurrences of key with repl for every (key, repl) pair in repl_pairs in each line of the given file and returns the lines of the file as a string.

Parameters:	file (File) – File handle for the file to read from. repl_pairs (list of (tuple of str)) – A list containing the `(key, repl)` pairs as tuples of strings.
Returns:	The content of the input file with all specified pairs replaced as a string.
Return type:	str