utils.verilog_utils module¶
-
utils.verilog_utils.
separateModules
(input_design, output_dir, f_files_in_dir=False, modules=None)¶ Extracts modules from a Verilog file and writes each in its own file.
The design file may contain annotations as specified by the AnnotatedCandidates FrontEnd implementation.
Parameters: - input_design (str) – The absolute path to the input circuit file in Verilog format.
- output_dir (str) – The absolute path to the directory in which to store the module circuit files.
- f_files_in_dir (bool, optional) – Specifies whether each output file is
placed in a folder with the module’s name (
True
) or directly in the output directory (False
). Default value isFalse
. - modules (list of str, optional) – A list specifying the names of the
modules to extract. If the list is empty or
None
, all modules are extracted. Otherwise, only the modules on the list are extracted. Default value isNone
.
-
utils.verilog_utils.
addModules
(input_design, output_design, modules)¶ Adds modules to a Verilog file. The file may contain annotations as specified by the AnnotatedCandidates FrontEnd implementation.
Parameters: - input_design (str) – The absolute path to the input circuit file in Verilog format.
- output_design (str) – The absolute path to the output circuit file.
- modules (list of str) – A list specifying the modules to add by specifying the absolute path to the circuit file which should be appended to the input circuit as a new module.
-
utils.verilog_utils.
removeModules
(input_design, output_design, modules)¶ Removes modules from a Verilog file. The file may contain annotations as specified by the AnnotatedCandidates FrontEnd implementation.
Parameters: - input_design (str) – The absolute path to the input circuit file in Verilog format.
- output_design (str) – The absolute path to the output circuit file.
- modules (list of str) – A list specifying the names of the modules to be removed.
-
utils.verilog_utils.
extractPisPos
(input_design, module, cand=None)¶ Extracts information about primary inputs and primary outputs from a Candidate’s Verilog file.
Parameters: - input_design (str) – The absolute path to the input circuit file in Verilog format.
- module (str) – The name of the module from which to extract the information.
- cand (
Candidate
, optional) – A Candidate instance can be specified to write the PI/PO information directly into the Candidate’s pis and pos attributes.
Returns: A list containing two lists of Signals, one for PIs and one for POs, if cand is
None
. OtherwiseNone
.Return type: (list of (list of
Signal
))Raises: ValueError
– If the specified module was not found.
-
utils.verilog_utils.
undoBitBlasting
(file_out, module, wrapper, pis, pos)¶ Wraps a module in a Verilog circuit file in a new module. The new module has restored busses. This might come in handy since bit-blasting might have lead to split up busses/vectors, e.g., when file has been converted to BLIF and back to Verilog.
Parameters: - file_out (str) – The absolute path to the output circuit file in Verilog format.
- module (str) – The name of the module to wrap.
- wrapper (str) – The name of the new wrapper module.
- pis (list of
Signal
) – A list containing the primary input Signals of the wrapped module. - pos (list of
Signal
) – A list containing the primary output Signals of the wrapped module.